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3.2 gbps sin g le buffered mux/demux switch AD8153 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features single lane 2:1 mux/1:2 demux 3.2 gbps to dc data rates compensates over 40 inches of fr4 at 3.2 gbps through two levels of input equalization, or four levels of output pre-emphasis operates with ac- or dc-coupled differential i/o low deterministic jitter, typically 16 ps p-p low random jitter, typically 500 fs rms on-chip terminations unicast or bicast on 1:2 demux function loopback capability on all ports 3.3 v core supply flexible i/o supply low power, typically 200 mw in basic configuration 1 32-lead lfcsp package ?40c to +85c operating temperature range applications low cost redundancy switch sonet oc48/sdh16 and lower data rates gigabit ethernet over backplane fibre channel 1.06 gbps and 2.12 gbps over backplane serial rapidio pci express gen 1 infiniband over backplane functional block diagram receive equalization transmit pre-emphasis 2:1 multiplexer/ 1:2 demultiplexer transmit pre-emphasis receive equalization control logic sel bicast lb_a lb_b lb_c mode resetb eq_a/(scl) eq_b/(sda) eq_c pe_a/(i2c_a[0]) pe_b/(i2c_a[1]) pe_c/(i2c_a[2]) input a input b output a output b output c input c AD8153 06393-001 eq eq eq figure 1. general description the AD8153 is an asynchronous, protocol agnostic, single-lane 2:1 switch with three differential cml inputs and three differential cml outputs. the ad8159, another member of the xstream line of products, is suitable for similar applications that require more than one lane. the AD8153 is optimized for nrz signaling with data rates of up to 3.2 gbps per port. each port offers two levels of input equalization and four levels of output pre-emphasis. the device consists of a 2:1 multiplexer and a 1:2 demultiplexer. there are three operating modes: pin mode, serial mode, and mixed mode. in pin mode, lane switching, equalization, and pre-emphasis are controlled exclusively using external pins. in serial mode, an i 2 c interface is used to control the device and to provide access to advanced features, such as additional pre- emphasis settings and output disable. in mixed mode, the user accesses the advanced features using i 2 c, but controls lane switching using the external pins. the main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. the device has unicast and bicast capability, so it is capable of supporting either 1 + 1 or 1:1 redundancy. using a mixture of bicast and loopback modes, the AD8153 can also be used to test high speed serial links by duplicating the incoming data and transmitting it to the destination port and test equipment simultaneously. 1 two ports active with no pre-emphasis.
AD8153 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 i 2 c timing specifications............................................................ 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 13 switch configurations ............................................................... 13 receive equalization .................................................................. 14 transmit pre-emphasis ............................................................. 14 i 2 c serial control interface........................................................... 15 register set.................................................................................. 15 general functionality ................................................................ 15 i 2 c data write............................................................................. 16 i 2 c data read.............................................................................. 17 applications information .............................................................. 18 pcb design guidelines ................................................................. 19 interfacing to the AD8153............................................................. 20 termination structures.............................................................. 20 input compliance....................................................................... 20 output compliance ................................................................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 4/07revision 0: initial version.
AD8153 rev. 0 | page 3 of 24 specifications v cc = v tti = v tto = 3.3 v, v ee = 0 v, r l = 50 , two outputs active with no pre-emphasis, data rate = 3.2 gbps, ac-coupled, prbs7 test pattern, v id = 800 mv p-p, t a = 25c, unless otherwise noted. 1 table 1. parameter conditions min typ max unit dynamic performance data rate/channel (nrz) dc 3.2 gbps deterministic jitter data rate = 3.2 gbps, high eq 16 ps p-p random jitter rms, high eq 500 fs propagation delay input to output 640 ps lane-to-lane skew 55 ps switching time 5 ns output rise/fall time 20% to 80% 85 ps input characteristics input voltage swing differential 200 2000 mv p-p input voltage range common mode, v id = 800 mv p-p v ee + 1.0 v cc + 0.3 v input capacitance 2 pf output characteristics output voltage swing differential, @ dc 700 800 900 mv p-p output voltage range single-ended absolute voltage level v cc ? 1.6 v cc + 0.6 v output current no pre-emphasis 16 ma output current maximum pre-emphasis, all ports 28 ma output capacitance 2 pf termination characteristics resistance differential 100 temperature coefficient 0.1 /c power supply operating range v cc v ee = 0 v 3.0 3.3 3.6 v v tti v ee = 0 v v cc v v tto v ee = 0 v v cc v 27 31 35 ma supply current i cc i i/o = i tto + i tti two outputs active, no pre-emphasis, 400 mv i/o swings (800 mv p-p differential) 26 32 39 ma 53 58 63 ma supply current i cc i i/o = i tto + i tti three outputs active, maximum pre-emphasis, 400 mv i/o swings (800 mv p-p differential) 74 84 95 ma thermal characteristics operating temperature range ?40 +85 c ja still air 30.0 c/w logic input characteristics input high (v ih ) 2.4 v cc v input low (v il ) v ee 0.8 v 1 v id : input differential voltage swing.
AD8153 rev. 0 | page 4 of 24 i 2 c timing specifications sda scl t f t low t hd;sta t r t hd;dat t high t su;dat t f t su;sta t hd;sta t sp t su;sto t r t buf s p sr s 06393-006 figure 2. i 2 c timing diagram table 2. parameter symbol min max unit scl clock frequency f scl 0 400+ khz hold time for a start condition t hd;sta 0.6 C s set-up time for a repeated start condition t su;sta 0.6 C s low period of the scl clock t low 1.3 C s high period of the scl clock t high 0.6 C s data hold time t hd;dat 0 C s data set-up time t su;dat 10 C ns rise time for both sda and scl t r 1 300 ns fall time for both sda and scl t f 1 300 ns set-up time for stop condition t su;sto 0.6 C s bus free time between a stop condition and a start condition t buf 1 C ns capacitance for each i/o pin c i 5 7 pf
AD8153 rev. 0 | page 5 of 24 absolute maximum ratings table 3. parameter rating v cc to v ee 3.7 v v tti v cc + 0.6 v v tto v cc + 0.6 v internal power dissipation 4.1 w differential input voltage 2.0 v logic input voltage v ee ? 0.3v < v in < v cc + 0.6 v storage temperature range ?65 c to +125 c lead temperature 300 c junction temperature 150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD8153 rev. 0 | page 6 of 24 pin configuration and function descriptions pin 1 indicator 1 vcc 2 vtto 3 ona 4 opa 5 vtti 6 ina 7 ipa 8 vee 24 mode 23 resetb 22 sel 21 bicast 20 lb_a 19 lb_b 18 lb_c 17 eq_a/(scl) 9 v c c 1 0 o n b 1 1 o p b 1 2 v c c 1 3 i n b 1 4 i p b 1 5 e q _ c 1 6 e q _ b / ( s d a ) 3 2 v e e 3 1 i p c 3 0 i n c 2 9 p e _ a / ( i 2 c _ a [ 0 ] ) 2 8 o p c 2 7 o n c 2 6 p e _ b / ( i 2 c _ a [ 1 ] ) 2 5 p e _ c / ( i 2 c _ a [ 2 ] ) 06393-002 AD8153 top view note epad needs to be electrically connected to vee. figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic type description 1, 9, 12 vcc power positive supply. 2 vtto power output termination supply. 3 ona i/o high speed output complement. 4 opa i/o high speed output. 5 vtti power input termination supply. 6 ina i/o high speed input complement. 7 ipa i/o high speed input. 8, 32, epad vee power negative supply. 10 onb i/o high speed output complement. 11 opb i/o high speed output. 13 inb i/o high speed input complement. 14 ipb i/o high speed input. 15 eq_c control port c input equalization control. 16 eq_b/(sda) control port b input equalization control/(i 2 c data when mode = 1). 17 eq_a/(scl) control port a input equalization control/(i 2 c clock when mode = 1). 18 lb_c control port c loopback enable. 19 lb_b control port b loopback enable. 20 lb_a control port a loopback enable. 21 bicast control bicast enable. 22 sel control a/b select. 23 resetb control configuration registers reset. 24 mode control configuration mode. 1 for serial/mixed mode, 0 for pin mode. 25 pe_c/(i2c_a[2]) control port c pre-emphasis control/(i 2 c slave address bit 2 when mode = 1). 26 pe_b/(i2c_a[1]) control port b pre-emphasis control/(i 2 c slave address bit 1 when mode = 1). 27 onc i/o high speed output complement. 28 opc i/o high speed output. 29 pe_a/(i2c_a[0]) control port a pre-emphasis control/(i 2 c slave address bit 0 when mode = 1). 30 inc i/o high speed input complement. 31 ipc i/o high speed output.
AD8153 rev. 0 | page 7 of 24 typical performance characteristics v cc = v tti = v tto =3.3 v, v ee = 0 v, r l = 50 , two outputs active with no pre-emphasis, high eq, data rate = 3.2 gbps, ac-coupled, prbs7 test pattern, v id = 800 mv p-p, t a = 25c, unless otherwise noted. 50? cables 2 2 high-speed sampling oscilloscope 50? cables 2 2 50? AD8153 ac coupled evaluation board input pin output pin pattern generator data out tp2 tp1 06393-014 figure 4. standard test circuit (no channel) 40ps/div 150mv/di v 06393-021 figure 5. 3.2 gbps input eye (tp1 from figure 4 ) 40ps/div 150mv/di v 06393-022 figure 6. 3.2 gbps output eye, no channel (tp2 from figure 4 )
AD8153 rev. 0 | page 8 of 24 50? cables 2 2 tp3 high- speed sampling oscilloscope 50? cables 2 2 50 ? AD8153 ac coupled evaluation board input pin output pin pattern generator data out tp1 50 ? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height trace lengths = 20 inches, 40 inches 06393-015 40ps/div 150mv/di v reference eye diagram at tp1 figure 7. input equalization test circuit 40ps/div 150mv/di v 06393-024 figure 8. 3.2 gbps input eye, 20 inch fr4 input channel (tp2 from figure 7 ) 40ps/div 150mv/di v 06393-025 figure 9. 3.2 gbps input eye, 40 inch fr4 input channel (tp2 from figure 7 ) 40ps/div 150mv/di v 06393-026 figure 10. 3.2 gbps output eye, 20 inch fr4 input channel, high eq (tp3 from figure 7 ) 40ps/div 150mv/di v 06393-027 figure 11. 3.2 gbps output eye, 40 inch fr4 input channel, high eq (tp3 from figure 7 )
AD8153 rev. 0 | page 9 of 24 50 ? cables 2 2 tp3 high- speed sampling oscilloscope 50 ? cables 2 2 50 ? AD8153 ac coupled evaluation board input pin output pin pattern generator data out tp1 50 ? cables 2 2 tp2 06393-013 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height trace lengths = 20 inches, 40 inches 40ps/div 150mv/di v reference eye diagram at tp1 figure 12. output pre-em phasis test circuit 40ps/div 150mv/di v 06393-017 figure 13. 3.2 gbps output eye, pre-channel, pe = 2 (tp2 from figure 12) 40ps/div 150mv/di v 06393-018 figure 14. 3.2 gbps output eye, pre-channel, pe = 3 (tp2 from figure 12) 40ps/div 150mv/di v 06393-019 figure 15. 3.2 gbps output eye, 20 inch fr4 output channel, pe = 2 (tp3 from figure 12) 40ps/div 150mv/di v 06393-020 figure 16. 3.2 gbps output eye, 40 inch fr4 output channel, pe = 3 (tp3 from figure 12)
AD8153 rev. 0 | page 10 of 24 80 70 60 50 40 30 20 10 0 deterministic jitter (ps) 06393-028 01 02 0 30 40 fr4 input channel length (in) high eq low eq figure 17. deterministic jitter vs. fr4 input channel length deterministic jitter random jitter 80 70 60 50 40 30 20 10 0 jitter (ps) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 data rate (gbps) 06393-038 figure 18. jitter vs. data rate 80 70 60 50 40 30 20 10 0 jitter (ps) 0 0.2 0.4 0.6 0.8 1.0 1.2 deterministic jitter random jitter 1.4 1.6 1.8 2.0 differential input swing (v) 06393-032 figure 19. jitter vs. differential input swing 80 70 60 50 40 30 20 10 0 deterministic jitter (ps) 0 1 02 03 04 fr4 output channel length (in) 06393-041 0 pe = 0 pe = 1 pe = 2 pe = 3 figure 20. deterministic jitter vs. fr4 output channel length 20 15 10 5 0 06393-039 ?2ps ?1ps 0.0s 1ps 2ps samples: 557k figure 21. random jitter histogram, 3.2 gbps 80 70 60 50 40 30 20 10 0 jitter (ps) 06393-035 0.8 1.3 1.8 2.3 2.8 3.3 3.8 input common-mode voltage (v) deterministic jitter random jitter figure 22. jitter vs. input common-mode voltage
AD8153 rev. 0 | page 11 of 24 80 70 60 50 40 30 20 10 0 jitter (ps) 06393-033 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc (v) deterministic jitter random jitter figure 23. jitter vs. core supply voltage ?40 ?20 0 20 40 60 80 100 temperature (c) deterministic jitter random jitter 80 70 60 50 40 30 20 10 0 jitter (ps) 06393-037 figure 24. jitter vs. temperature 700 600 650 550 500 propag a tion del a y (ps) 06393-030 3.0 3.1 3.2 3.3 3.4 v cc (v) 3.5 3.6 figure 25. propagation delay vs. core supply voltage deterministic jitter random jitter 80 70 60 50 40 30 20 10 0 jitter (ps) 2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vtto (v) 06393-031 figure 26. jitter vs. output termination voltage 100 95 90 85 80 75 rise/fall time (ps) ?40 ?20 0 20 40 60 80 100 temperature (c) 06393-029 figure 27. rise/fall time vs. temperature ?40 ?20 0 20 40 60 80 100 temperature (c) 06393-040 700 600 650 550 500 propag a tion del a y (ps) figure 28. propagation delay vs. temperature
AD8153 rev. 0 | page 12 of 24 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc (v) 1000 900 800 700 600 500 400 300 200 100 0 eye height (mv) 06393-034 figure 29. eye height vs. core supply voltage 1000 900 800 700 600 500 400 300 200 100 0 eye height (mv) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 data rate (gbps) 06393-036 figure 30. eye height vs. data rate
AD8153 rev. 0 | page 13 of 24 theory of operation the AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer. there are three operating modes: pin mode, serial mode, and mixed mode. in pin mode, lane switching, equalization, and pre-emphasis are controlled using external pins. in serial mode, an i 2 c interface is used to control the device and to provide access to advanced features, such as additional pre-emphasis settings and output disable. in mixed mode, the user accesses the advanced features using i 2 c but controls lane switching using external pins. switch configurations on the demultiplexer side, the AD8153 relays received data on input port c to output port a and/or output port b, depending on the state of the bicast and sel bits. on the multiplexer side, the device relays received data on either input port a or input port b to output port c, depending on the state of the sel bit. when bicast mode is off, the outputs of either port a or port b are in an idle state. in the idle state, the output tail current is set to 0, and the p and n sides of the lane are pulled up to the output termination voltage through the on-chip termination resistors. the device also supports loopback on all ports, illustrated in figure 31 . enabling loopback on any port overrides configurations set by the bicast and sel control bits. table 5 summarizes the possible switch configurations. the AD8153 output disable feature can be used to force an output into the idle (powered-down) state. this feature is only accessible through the serial control interface. 1:2 demux 2:1 mux input c output c port c looplock output a output b input a input b port a loopback port b loopback 06393-003 figure 31. loopback configurations table 5. switch configurations lb_a lb_b lb_c sel bicast output a output b output c 0 0 0 0 0 input c idle input a 0 0 0 0 1 input c input c input a 0 0 0 1 0 idle input c input b 0 0 0 1 1 input c input c input b 0 0 1 0 0 input c idle input c 0 0 1 x 1 input c input c input c 0 0 1 1 0 idle input c input c 0 1 0 0 x input c input b input a 0 1 0 1 0 idle input b input b 0 1 0 1 1 input c input b input b 0 1 1 0 x input c input b input c 0 1 1 1 0 idle input b input c 0 1 1 x 1 input c input b input c 1 0 0 0 0 input a idle input a 1 0 0 0 1 input a input c input a 1 0 0 1 x input a input c input b 1 0 1 0 0 input a idle input c
AD8153 rev. 0 | page 14 of 24 lb_a lb_b lb_c sel bicast output a output b output c 1 0 1 x 1 input a input c input c 1 0 1 1 x input a input c input c 1 1 0 0 x input a input b input a 1 1 0 1 x input a input b input b 1 1 1 x x input a input b input c receive equalization in backplane applications, the AD8153 needs to compensate for signal degradation caused by long traces. the device supports two levels of input equalization, configured on a per-port basis. table 6 summarizes the high-frequency asymptotic gain boost for each setting. table 6. receive equalization settings eq_a/b/c eq boost 0 6 db 1 12 db transmit pre-emphasis transmitter pre-emphasis levels can be set by pin control or through the control registers when using the i 2 c interface. pin control allows two settings of pe. the control registers provide two additional settings. table 7. pre-emphasis settings serial mode pin mode pe_a/b/c setting pe_a/b/c pe boost (%) pe boost (db) 0 0 0 0 1 n/a 25 1.9 2 1 50 3.5 3 n/a 75 4.9
AD8153 rev. 0 | page 15 of 24 i 2 c serial control interface register set the AD8153 can be controlled in one of three modes: pin mode, serial mode, and mixed mode. in pin mode, the AD8153 control is derived from the package pins, whereas in serial mode a set of internal registers controls the AD8153. there is also a mixed mode where switching is controlled via external pins, and equalization and pre-emphasis are controlled via the internal registers. the methods for writing data to and reading data from the AD8153 are described in the i 2 c data write section and the i 2 c data read section. the mode is controlled via the mode pin. to set the part in pin mode, mode should be driven low to vee. when mode is driven high to vcc, the part is set to serial or mixed mode. in pin mode, all controls are derived from the external pins. in serial mode, each channels equalization and pre-emphasis are controlled only through the registers, as described in table 8 . additionally, further functionality is available in serial mode as each channels output can be enabled/disabled with the output enable control bits, which is not possible in pin mode. to change the switching in the AD8153 to serial mode, the mask bits (register 0x00) must be set to 1 by writing the value 0x1f to this register, as explained in the following sections. once all the mask bits are set to 1, switching is controlled via the lb_a, lb_b, lb_c, sel, and bicast bits in the register set. in mixed mode, each channels equalization and pre-emphasis are controlled through the registers as described above. the switching, however, can be controlled using either the external pins or the internal register set. the source of the control is selected using the mask bits (register 0x00). if a mask bit is set to 0, the external pin acts as the source for that specific control. if a mask bit is set to 1, the associated internal register acts as the source for that specific control. as an example, if register 0x00 were set to the value 0x0c, the sel and lb_c controls would come from the internal register set (bit 0 of register 0x04 and bit 3 of register 0x03, respectively), and the bicast, lb_a, and lb_b controls would come from the external pins. general functionality the AD8153 register set is controlled through a 2-wire i 2 c interface. the AD8153 acts only as an i 2 c slave device. therefore, the i 2 c bus in the system needs to include an i 2 c master to configure the AD8153 and other i 2 c devices that may be on the bus. when the mode pin is set to a logic 1, data transfers are controlled through the use of the two i 2 c wires: the input clock pin, scl, and the bidirectional data pin, sda. the AD8153 i 2 c interface can be run in the standard (100 khz) and fast (400 khz) modes. the sda line only changes value when the scl pin is low with two exceptions. to indicate the beginning or continuation of a transfer, the sda pin is driven low while the scl pin is high, and to indicate the end of a transfer, the sda line is driven high while the scl line is high. therefore, it is important to control the scl clock to only toggle when the sda line is stable unless indicating a start, repeated start, or stop condition. table 8. register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 00000000 (0x00) bicast mask sel mask lb_c mask lb_b mask lb_a mask 00000000 (0x00) 00000001 (0x01) output disable a lb_a eq_a pe_a [1] pe_a [0] 00000000 (0x00) 00000010 (0x02) output disable b lb_b eq_b pe_b [1] pe_b [0] 00000000 (0x00) 00000011 (0x03) output disable c lb_c eq_c pe_c [1] pe_c [0] 00000000 (0x00) 0000100 (0x04) bicast sel 00000000 (0x00)
AD8153 rev. 0 | page 16 of 24 i 2 c data write to write data to the AD8153 register set, a microcontroller, or any other i 2 c master, needs to send the appropriate control signals to the AD8153 slave device. the steps that need to be followed are listed below, where the signals are controlled by the i 2 c master unless otherwise specified. a diagram of the procedure is shown in figure 32 . 1. send a start condition (while holding the scl line high, pull the sda line low). 2. send the AD8153 part address (seven bits) whose upper four bits are the static value b1001 and whose lower three bits are controlled by the input pins i2c_a[2:0]. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the AD8153 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the AD8153 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the AD8153 to acknowledge the request. 9. send a stop condition (while holding the scl line high, pull the sda line high) and release control of the bus. 10. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 in this procedure to perform another write. 11. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of the read procedure (in the i 2 c data read section) to perform a read from another address. 12. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of the read procedure (in the i 2 c data read section) to perform a read from the same address set in step 5. the AD8153 write process is shown in figure 32 . the scl signal is shown along with a general write operation and a specific example. in the example, data 0x92 is written to address 0x6d of an AD8153 part with a part address of 0x4b. the part address is seven bits wide and is composed of the AD8153 static upper four bits (b1001) and the pin programmable lower three bits (i2c_addr[2:0]). in this example, the i2c_addr bits are set to b011. in figure 32 , the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master and never by the AD8153 slave. as for the sda line, the data in the shaded polygons is driven by the AD8153, whereas the data in the non- shaded polygons is driven by the i 2 c master. the end phase case shown is that of 9a. it is important to note that the sda line only changes when the scl line is low, except for the case of sending a start, stop, or repeated start condition, step 1 and step 9 in this case. scl sda (general case) sda (example) start fixed part addr addr [2:0] rw ack register addr ack data ack stop 12 34 2567 06393-004 8 9 a figure 32. i 2 c write diagram
AD8153 rev. 0 | page 17 of 24 i 2 c data read to read data from the AD8153 register set, a microcontroller, or any other i 2 c master, needs to send the appropriate control signals to the AD8153 slave device. the steps to be followed are listed below, where the signals are controlled by the i 2 c master unless otherwise specified. a diagram of the procedure can be seen in figure 33 . 1. send a start condition (while holding the scl line high, pull the sda line low). 2. send the AD8153 part address (seven bits) whose upper four bits are the static value b1001 and whose lower three bits are controlled by the input pins i2c_addr[2:0]. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the AD8153 to acknowledge the request. 5. send the register address (eight bits) from which data is to be read. this transfer should be msb first. the register address is kept in memory in the AD8153 until the part is reset or the register address is written over with the same procedure (step 1 to step 6). 6. wait for the AD8153 to acknowledge the request. 7. send a repeated start condition (while holding the scl line high, pull the sda line low). 8. send the AD8153 part address (seven bits) whose upper four bits are the static value b1001 and whose lower three bits are controlled by the input pins i2c_addr[1:0]. this transfer should be msb first. 9. send the read indicator bit (1). 10. wait for the AD8153 to acknowledge the request. 11. the AD8153 then serially transfers the data (eight bits) held in the register indicated by the address set in step 5. 12. acknowledge the data. 13. send a stop condition (while holding the scl line high, pull the sda line high) and release control of the bus. 14. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of the write procedure (see the i 2 c data write section) to perform a write. 15. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of this procedure to perform a read from another address. 16. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of this procedure to perform a read from the same address. the AD8153 read process is shown in figure 33 . the scl signal is shown along with a general read operation and a specific example. in the example, data 0x49 is read from address 0x6d of an AD8153 part with a part address of 0x4b. the part address is seven bits wide and is composed of the AD8153 static upper four bits (b1001) and the pin programmable lower three bits (i2c_addr[2:0]). in this example, the i2c_addr bits are set to b011. in figure 33 , the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master and never by the AD8153 slave. as for the sda line, the data in the shaded polygons is driven by the AD8153, whereas the data in the nonshaded polygons is driven by the i 2 c master. the end phase case shown is that of 13a. it is important to note that the sda line only changes when the scl line is low, except for the case of sending a start, stop, or repeated start condition, as in step 1, step 7, and step 13. in figure 33 , a is the same as ack in figure 32 . equally, sr represents a repeated start where the sda line is brought high before scl is raised. sda is then dropped while scl is still high. scl sda (general case) sda (example) start fixed part addr addr [2:0] r w a register addr a data a stop 12 34 256 7 89 06393-005 10 11 12 13a 8 sr fixed part addr addr [2:0] r w a figure 33. i 2 c read diagram
AD8153 rev. 0 | page 18 of 24 applications information the main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. figure 34 illustrates redundancy in a typical backplane system. each line card is connected to two switch fabrics (primary and redundant). the device can be configured to support either 1 + 1 or 1:1 redundancy. another application for the AD8153 is in test equipment for evaluating high speed serial links. figure 36 illustrates a possible application of the AD8153 in a simple link tester. fabric cards line cards backplane AD8153 physical interface AD8153 physical interface 06393-007 redundant switch fabric primary switch fabric digital engine digital engine figure 34. switch redundancy application processing engine/crossbar/ backplane 06393-008 AD8153 sfp sfp cdr cdr figure 35. line interface redundancy application protocol analyzer fpga dut 06393-009 connector connector AD8153 figure 36. test equipment application
AD8153 rev. 0 | page 19 of 24 pcb design guidelines proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane is recommended. the vee pins should be soldered directly to the ground plane to reduce series inductance. if the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. the exposed pad should be connected to the vee plane using plugged vias so that solder does not leak through the vias during reflow. use of a 10 f electrolytic capacitor between vcc and vee is recommended at the location where the 3.3 v supply enters the pcb. it is recommended that 0.1 f and 1 nf ceramic chip capacitors be placed in parallel at each supply pin for high frequency power supply decoupling. when using 0.1 f and 1 nf ceramic chip capacitors, they should be placed between the ic power supply pins (vcc, vtti, vtto) and vee, as close as possible to the supply pins. by using adjacent power supply and gnd planes, excellent high frequency decoupling can be realized by using close spacing between the planes. this capacitance is given by c plane = 0.88 r a/d (pf) where: r is the dielectric constant of the pcb material. a is the area of the overlap of power and gnd planes (cm 2 ). d is the separation between planes (mm). for fr4, r = 4.4 and 0.25 mm spacing, c ~15 pf/cm 2 . transmission lines use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections. it is also necessary for the high speed pairs of differential input traces to be matched in length, as well as the high speed pairs of differential output traces, to avoid skew between the differential traces. soldering guidelines for chip scale package the lands on the 32-lead lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central exposed pad. the pad on the printed circuit board should be at least as large as this exposed pad. the user must connect the exposed pad to vee using plugged vias so that solder does not leak through the vias during reflow. this ensures a solid connection from the exposed pad to vee.
AD8153 rev. 0 | page 20 of 24 interfacing to the AD8153 termination structures to determine the best strategy for connecting to the high speed pins of the AD8153, the user must first be familiar with the on- chip termination structures. the AD8153 contains two types of these structures: one type for input ports and one type for output ports (see figure 37 and figure 38 ). v c c vtti ipx inx vee 55 ? 55? 1173? 06393-010 figure 37. receiver simplified diagram vcc vtto opx onx vee 50 ? 06393-011 50? v ip v in i t figure 38. transmitter simplified diagram for input ports, the termination structure consists of two 55 resistors connected to a termination supply and an 1173 resistor connected across the differential inputs, the latter being a result of the finite differential input impedance of the equalizer. for output ports, there are two 50 resistors connected to the termination supply. note that the differential input resistance for both structures is the same, 100 . input compliance the range of allowable input voltages is determined by the fundamental limitations of the active input circuitry. this range of signals is normally a function of the common-mode level of the input signal, the signal swing, and the supply voltage. for a given input signal swing, there is a range of common-mode voltages that keeps the high and low voltage excursions within acceptable limits. similarly, for a given common-mode input voltage, there is a maximum acceptable input signal swing. there is also a minimum signal swing that the active input circuitry can resolve reliably. the specifications are found in table 1 . ac coupling one way to simplify the input circuit and make it compatible with a wide variety of driving devices is to use ac coupling. this has the effect of isolating the dc common-mode levels of the driver and the AD8153 input circuitry. ac coupling requires a capacitor in series with each single-ended input signal, as shown in figure 39 . this should be done in a manner that does not interfere with the high speed signal integrity of the pcb. 06393-042 50 ? 50? v cc v cc 55 ? v tti driver AD8153 55? vee 1173 ? c p c n ip in figure 39. ac-coupling input signal of AD8153 when ac coupling is used, the common-mode level at the input of the device is equal to v tti . the single-ended input signal swings above and below v tti equally. the user can then use the specifications in table 1 to determine the input signal swing levels that satisfy the input range of the AD8153. if dc coupling is required, determining the input common- mode level is less straightforward because the configuration of the driver must also be considered. in most cases, the user would set v tti on the AD8153 to the same level as the driver output termination voltage. this prevents a continuous dc current from flowing between the two supply nets. as a practical matter, both devices can be terminated to the same physical supply net. consider the following example: a driver is dc-coupled to the input of the AD8153. the AD8153 input termination voltage (v tti ) and the driver output termination voltage (v ttod ) are both set to the same level; that is, v tti = v ttod = 3.3 v. if an 800 mv differential p-p swing is desired, the total output current of the driver is 16 ma. at balance, the output current is divided evenly between the two sides of the differential signal path, 8 ma to each side. this 8 ma of current flows through the parallel combina- tion of the 55 input termination resistor on the AD8153 and the 50 output termination resistor on the driver, resulting in a common-mode level of v tti ? 8 ma u ( 50 55 ) = v tti ? 209 mv the user can then determine the allowable range of values for v tti that meets the input compliance range based on an 800 mv p-p differential swing.
AD8153 rev. 0 | page 21 of 24 output compliance figure 40 is a graphical depiction of the single-ended waveform at the output of the AD8153. the common-mode level (v ocm ) and the amplitude (v ose ) of this waveform are a function of the output tail current (i t ), the output termination supply voltage (v tto ), the topology of the far-end receiver, and whether ac- or dc-coupling is used. keep in mind that the output tail current varies with the pre-emphasis level. the user must ensure that the high (v h ) and low (v l ) voltage excursions at the output are within the single-ended absolute voltage range limits as specified in table 1 . failure to understand the implications of output signal levels and the choice of ac- or dc-coupling may lead to transistor saturation and poor transmitter performance. table 9 shows an example calculation of the output levels for the typical case, where v cc = v tto = 3.3 v, with 50 far-end terminations to a 3.3 v supply. 06393-012 v ocm v h v l v ose-dc v ose-boost v tto ~320ps figure 40. single-ended output waveform table 9. output voltage levels dc-coupled ac-coupled pe setting i t (ma) v ose-dc (mv p-p) v ose-boost (mv p-p) v ocm (v) v h (v) v l (v) v ocm (v) v h (v) v l (v) 0 16 400 400 3.1 3.3 2.9 2.9 3.1 2.7 1 20 400 500 3.05 3.3 2.8 2.8 3.05 2.55 2 24 400 600 3 3.3 2.7 2.7 3 2.4 3 28 400 700 2.95 3.3 2.6 2.6 2.95 2.25 table 10. symbol definitions symbol formula definition v ose-dc ? = pe t i single-ended output voltage swing after settling v ose-boost ? 25 t i boosted single-ended output voltage swing v ocm (dc-coupled) ?? 25 2 t tto i v common-mode voltage when the output is dc-coupled v ocm (ac-coupled) ?? 50 2 t tto i v common-mode voltage when the output is ac-coupled v h v ocm + v ose-boost /2 high single-ended output voltage excursion v l v ocm - v ose-boost /2 low single-ended output voltage excursion
AD8153 rev. 0 | page 22 of 24 outline dimensions 032807-a compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min * exposed pad (bot tom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq * the AD8153 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to v ee . it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. figure 41. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-8) dimensions shown in millimeters ordering guide model temperature range package description package option AD8153acpz 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 AD8153acpz-rl7 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 AD8153-evalz 1 evaluation board 1 z = rohs compliant part.
AD8153 rev. 0 | page 23 of 24 notes
AD8153 rev. 0 | page 24 of 24 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06393-0-4/07(0)

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